The invention generally relates to electronic power supplies, and more specifically, to pulse modulation in a switching voltage regulator.
Pulse-controlled switching voltage regulators, such as constant off-time/on-time regulators, have the advantage of short reaction time to transient conditions and simplicity of operation. FIG. 1 shows a typical constant off-time step-down switching voltage regulator. The regulator 10 provides a regulated DC voltage VOUT at terminal 17 to drive a load 18. Driver circuit 20 synchronously drives push-pull power switch 30, which includes p-channel MOSFET 32 and n-channel MOSFET 34. Output circuit 40 includes an output inductor 41 and an output capacitor 42, which act together as a filter that smoothes the output ripple current.
A control circuit 50 acts upon the driver circuit 20 and power switch 30 to regulate the output voltage at terminal 17. Control circuit 50 includes the feedback resistor dividers R51A and R51B that generate a feedback signal VFB proportional to VOUT, a reference circuit 52, a feedback comparator 53, and constant off-time one shot 54. The control circuit 50 operates to force the reference voltage VREF upon the feedback voltage VFB, thereby controlling the output voltage VOUT. When VFB is less than VREF, the output of comparator 53 is low, and output of one shot 54 also is low. Driver circuit 20 provides a low level to turn on the p-channel MOSFET 32, and turn off the n-channel MOSFET 34. This condition will be referred to as the power switch 30 being xe2x80x9conxe2x80x9d. Power switch 30 then applies the input voltage VIN to the output circuit 40, increasing the inductor current and charging the output capacitor 42, while providing power to the load 18.
This situation continues until VFB exceeds VREF. At that point, the comparator 53 generates a signal to trigger the one shot 54. One shot 54 in turn provides a high level pulse to the driver circuit 20 to turn off the power switch 30. This causes a decrease in the current provided to the output circuit 40, thus decreasing the output voltage VOUT.
At the termination of the pulse from one shot 54, the power switch 30 turns on again and the cycle repeats. This operation causes a small output ripple in VOUT. The down slope of the ripple is constant and directly proportional to the duration of the off-time pulse TOFF from one shot 54. The up slope of the ripple is proportional to the on-time of the power switch 30.
One drawback of this approach is the undesirable variation in the frequency due to variation in on-time of power switch 30. On-time is proportional to input voltage VIN, output voltage VOUT, and other factors such as voltage drops across power switch 30 and printed circuit trace resistance. For example, if the difference between VIN and VOUT doubles, then the on-time of power switch 30 will halve. Switching frequency, however, will change less because it involves both on- and off-times. Nevertheless, conditions could cause switching frequency to vary by more than 300%. This wide frequency variation translates into output ripple variation, and degrades the overall performance of the voltage regulator 10.
Another disadvantage of the traditional prior art is the occasional overly extended on-time. The power switch 30 remains on until VFB reaches VREF. In applications where the p-channel MOSFET 32 is replaced with an n-channel MOSFET, a scheme called xe2x80x9cbootstrapxe2x80x9d is commonly used. In bootstrapping, as power switch 30 alternates between on and off, an external capacitor is used to provide enough voltage for the top n-channel MOSFET to properly conduct current. This requires continued switching. If the control circuit 50 creates an overly extended on-time, the bootstrap operation will be defeated. This will result in a loss of sufficient drive to the top MOSFET, and collapse of the output voltage VOUT.
Yet another disadvantage of the prior art as shown in FIG. 1 is the inability to detect light load conditions and turn off the power switch 30 under such conditions. This should be done in order to reduce switching losses and prevent output capacitor discharge, thus increasing overall efficiency at light loads.
The circuit in FIG. 1 proves stable and simple to implement in buck switching regulators, where input voltage is higher than output voltage. However, the attendant frequency variation may not be acceptable in some applications needing optimized external components. In some applications, for example, the external components may be selected based on performance, specification, and cost, to provide a given output ripple voltage at a specified frequency. If the frequency varies unreasonably, the output ripple will degrade from optimum to less than optimum.
A need arises for a pulse modulation approach that compensates for frequency variation so as to keep output ripple at optimum level. Additionally, a constant frequency may be needed where it is important to avoid noise sensitive regions such as the 455 KHz IF band.
FIG. 2 shows one prior art attempt, described in U.S. Pat. No. 5,994,885 (incorporated herein by reference), to address some of these issues via off-time modulation. Off time control 230 receives signals from both the input voltage VIN, and the output voltage VOUT. An internal algorithm is then used to modulate a control current ICON that discharges off-time capacitor CCON. This generates a variable duration pulse at the output of one shot generator 245. As VIN increases relative to VOUT, on-time is reduced. This can be understood by examining the equation:       T    ON    =      L    ⁡          (                        I          L                          V          L                    )      
where L is inductance, IL is inductor current, and VL is voltage across the inductor. To compensate for reduction in the switch on-time, off-time control circuit 230 reduces the off-time discharge current ICON to increase the discharge time of CCON. This causes an increase in the switch off-time. Similarly, when VIN decreases relative to VOUT, switch on-time increases. The off time control 230 increases the discharge current ICON to reduce the discharge time of CCON, thus reducing the switch off-time. The net result is reduced variation in the apparent operating frequency.
One disadvantage of this approach, however, is the need for physical connections to VIN and VOUT. In most applications, feedback resistor divider 210 is set externally. So for a true connection to VOUT, an additional external terminal is needed. Another disadvantage is the lack of a refresh pulse needed for bootstrap applications where a capacitor needs to be continually switched in order to provide sufficient drive to the top n-channel MOSFET. Yet another disadvantage is the failure to take into effect other factors that influence frequency variation, such as but not limited to switch and trace resistance.
Representative embodiments of the present invention variously include a control circuit for a switching voltage regulator, a method of controlling a switching voltage regulator, and a switching voltage regulator. A power switching module operates at a duty cycle and provides a regulated output. A feedback circuit produces a feedback signal representative of the regulated output. A timing control circuit produces a timing signal responsive to the duty cycle of the power switching module. A control module is triggered by the feedback signal to produce an output pulse to control the regulated output. The output pulse has a duration determined by the timing signal.
In a further embodiment, the control module may be based on a constant off-time approach, or a constant on-time approach. The timing control circuit may sense the regulator duty cycle at the output of the control module, at the power switching module, or from voltage ripple in the feedback signal. A control capacitance responsive to the duty cycle may be used to produce the timing signal. In such an embodiment, the control capacitance may be charged or discharged at a rate responsive to the duty cycle. Alternatively, a control capacitor may be charged at a rate responsive to the duty cycle.
A further embodiment may include a maximum duty cycle comparator to cause a change in a logic state of the output pulse after an over-extended period of time when the duty cycle is greater than during normal regulator operation. Yet another embodiment may include a minimum duty cycle comparator to place the power stage into a high impedance state after an over-extended period of time when the duty cycle is less than during normal regulator operation, so as to increase overall efficiency of the regulator under light loads.
In one embodiment, a duty cycle voltage is produced that is representative of the duty cycle. In addition or alternatively, a pulse duration voltage may be produced that is representative of the duration of the output pulse. The timing signal may be further responsive to the duration of the output pulse.
In any of the above embodiments, the off-time of the regulator may be inversely proportional to either the duty cycle or duration of the output pulse, so as to maintain a constant operating frequency. Alternatively, the on-time may be proportional to the duty cycle so as to maintain a constant operating frequency.